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| Synchronous Buck Controller with Constant On-Time and Valley Current Mode ADP1870/ADP1871 FEATURES Power input voltage range: 2.95 V to 20 V On-board bias regulator Minimum output voltage: 0.6 V 0.6 V reference voltage with 1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 kHz, and 1.0 MHz options No current-sense resistor required Power saving mode (PSM) for light loads (ADP1871 only) Resistor-programmable current-sense gain Thermal overload protection Short-circuit protection Precision enable input Integrated bootstrap diode for high-side drive Starts into a precharged load Small, 10-lead MSOP package TYPICAL APPLICATIONS CIRCUIT VIN = 2.95V TO 20V CC RTOP RC CC2 VIN ADP1870/ ADP1871 COMP/EN BST CBST FB DRVH SW CIN VOUT Q1 L VOUT RBOT GND CVREG2 COUT Q2 RRES LOAD VREG DRVL PGND CVREG Figure 1. 100 95 90 85 80 EFFICIENCY (%) VIN = 5V (PSM) APPLICATIONS Telecom and networking systems Mid to high end servers Set-top boxes DSP core power supplies 75 70 65 60 55 50 45 40 VIN = 16.5V (PSM) 35 30 25 10 100 VIN = 13V (PSM) TA = 25C VOUT = 1.8V fSW = 300kHz WURTH INDUCTOR: 744325120, L = 1.2H, DCR = 1.8m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 1k LOAD CURRENT (mA) 10k 100k 08730-102 VIN = 16.5V VIN = 13V GENERAL DESCRIPTION The ADP1870/ADP1871 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current-limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentlimit, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by utilizing valley current-mode control architecture. This allows the ADP1870/ ADP1871 to drive all N-channel power stages to regulate output voltages as low as 0.6 V. The ADP1871 is the power saving mode (PSM) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the Power Saving Mode (PSM) Version (ADP1871) section for more information). Available in three frequency options (300 kHz, 600 kHz, and 1.0 MHz, plus the PSM option), the ADP1870/ADP1871 are well suited for a wide range of applications that require a single-input power supply range from 2.95 V to 20 V. Low voltage biasing is supplied via a 5 V internal LDO. Figure 2. Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz) In addition, an internally fixed soft start period is included to limit input in-rush current from the input supply during startup and to provide reverse current protection during soft start for a precharged output. The low-side current-sense, current-gain scheme and integration of a boost diode, along with the PSM/forced pulsewidth modulation (PWM) option, reduce the external part count and improve efficiency. The ADP1870/ADP1871 operate over the -40C to +125C junction temperature range and are available in a 10-lead MSOP package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved. 08730-001 ADP1870/ADP1871 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Applications Circuit............................................................ 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Boundary Condition .................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 ADP1870/ADP1871 Block Diagram............................................ 18 Theory of Operation ...................................................................... 19 Startup .......................................................................................... 19 Soft Start ...................................................................................... 19 Precision Enable Circuitry ........................................................ 19 Undervoltage Lockout ............................................................... 19 On-Board Low Dropout Regulator .......................................... 19 Thermal Shutdown..................................................................... 20 Programming Resistor (RES) Detect Circuit .......................... 20 Valley Current-Limit Setting .................................................... 20 Hiccup Mode During Short Circuit ......................................... 21 Synchronous Rectifier ................................................................ 22 Power Saving Mode (PSM) Version (ADP1871) ................... 22 Timer Operation ........................................................................ 22 Pseudo-Fixed Frequency ........................................................... 23 Applications Information .............................................................. 24 Feedback Resistor Divider ........................................................ 24 Inductor Selection ...................................................................... 24 Output Ripple Voltage (VRR) .................................................. 24 Output Capacitor Selection....................................................... 24 Compensation Network ............................................................ 25 Efficiency Considerations ......................................................... 26 Input Capacitor Selection .......................................................... 27 Thermal Considerations............................................................ 28 Design Example .......................................................................... 29 External Component Recommendations .................................... 31 Layout Considerations ................................................................... 33 IC Section (Left Side of Evaluation Board) ............................. 37 Power Section ............................................................................. 37 Differential Sensing .................................................................... 38 Typical Applications Circuits ........................................................ 39 15 A, 300 kHz High Current Application Circuit .................. 39 5.5 V Input, 600 kHz Application Circuit ............................... 39 300 kHz High Current Application Circuit ............................ 40 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 41 REVISION HISTORY 3/10--Revision 0: Initial Version Rev. 0 | Page 2 of 44 ADP1870/ADP1871 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V, VBST - VSW = VREG - VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = -40C to +125C, unless otherwise specified. Table 1. Parameter POWER SUPPLY CHARACTERISTICS High Input Voltage Range Symbol VIN Conditions CIN = 22 F to PGND (at Pin 1) ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz) ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz) ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz) VFB = 1.5 V, no switching COMP/EN < 285 mV Rising VIN (see Figure 35 for temperature variation) Falling VIN from operational state Min Typ Max Unit 2.95 2.95 3.25 Quiescent Current Shutdown Current Undervoltage Lockout UVLO Hysteresis INTERNAL REGULATOR CHARACTERISTICS VREG Operational Output Voltage IQ_REG + IQ_BST IREG,SD + IBST,SD UVLO 12 12 12 1.1 190 2.65 190 20 20 20 280 V V V mA A V mV VREG VREG Output in Regulation Load Regulation Line Regulation VIN to VREG Dropout Voltage Short VREG to PGND SOFT START Soft Start Period ERROR AMPLIFER FB Regulation Voltage CVREG = 1 F to PGND, 0.22 F to GND, VIN = 2.95 V to 20 V ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz) ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz) ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz) VIN = 7 V, 100 mA VIN = 12 V, 100 mA 0 mA to 100 mA, VIN = 7 V 0 mA to 100 mA, VIN = 20 V VIN = 7 V to 20 V, 20 mA VIN = 7 V to 20 V, 100 mA 100 mA out of VREG, VIN 5 V VIN = 20 V See Figure 58 2.75 2.75 3.05 4.8 4.8 5 5 5 4.981 4.982 32 33 2.5 2.0 300 229 3.0 600 600 600 496 1 3 6 12 24 5.5 5.5 5.5 5.16 5.16 415 320 V V V V V mV mV mV mV mV mA ms mV mV mV S nA V/V V/V V/V V/V VFB TJ = +25C TJ = -40C to +85C TJ = -40C to +125C VFB = 0.6 V, COMP/EN = released RES = 47 k 1% RES = 22 k 1% RES = none RES = 100 k 1% Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation 1 Transconductance FB Input Leakage Current CURRENT-SENSE AMPLIFIER GAIN Programming Resistor (RES) Value from DRVL to PGND Gm IFB, Leak 596 594.2 320 604 605.8 670 50 3.3 6.5 13 26 2.7 5.5 11 22 SWITCHING FREQUENCY ADP1870ARMZ-0.3/ ADP1871ARMZ-0.3 (300 kHz) On-Time Minimum On-Time Minimum Off-Time 300 VIN = 5 V, VOUT = 2 V, TJ = 25C VIN = 20 V 84% duty cycle (maximum) 1120 1200 146 340 1280 190 400 kHz ns ns ns Rev. 0 | Page 3 of 44 ADP1870/ADP1871 Parameter ADP1870ARMZ-0.6/ ADP1871ARMZ-0.6 (600 kHz) On-Time Minimum On-Time Minimum Off-Time ADP1870ARMZ-1.0/ ADP1871ARMZ-1.0 (1.0 MHz) On-Time Minimum On-Time Minimum Off-Time OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance Rise Time 2 Fall Time2 Low-Side Driver Output Source Resistance Output Sink Resistance Rise Time2 Fall Time2 Propagation Delays DRVL Fall to DRVH Rise2 DRVH Fall to DRVL Rise2 SW Leakage Current Integrated Rectifier Channel Impedance PRECISION ENABLE THRESHOLD Logic High Level Enable Hysteresis COMP VOLTAGE COMP Clamp Low Voltage COMP Clamp High Voltage COMP Zero Current Threshold THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Hiccup Current Limit Timing 1 Symbol Conditions Min Typ 600 540 82 340 1.0 312 60 340 Max Unit kHz ns ns ns MHz ns ns ns VIN = 5 V, VOUT = 2 V, TJ = 25C VIN = 20 V, VOUT = 0.8 V 65% duty cycle (maximum) 500 580 110 400 VIN = 5 V, VOUT = 2 V, TJ = 25C VIN = 20 V 45% duty cycle (maximum) 285 340 85 400 tr,DRVH tf,DRVH ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) VBST - VSW = 4.4 V, CIN = 4.3 nF (see Figure 60) VBST - VSW = 4.4 V, CIN = 4.3 nF (see Figure 61) ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) VREG = 5.0 V, CIN = 4.3 nF (see Figure 61) VREG = 5.0 V, CIN = 4.3 nF (see Figure 60) VBST - VSW = 4.4 V (see Figure 60) VBST - VSW = 4.4 V (see Figure 61) VBST = 25 V, VSW = 20 V, VREG = 5 V ISINK = 10 mA VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 245 2.25 0.7 25 11 1.6 0.7 18 16 15.4 18 3 1 ns ns ns ns ns ns A 2.2 1 tr,DRVL tf,DRVL ttpdhDRVH ttpdhDRVL ISWLEAK 110 22 285 37 330 mV mV V VCOMP(low) VCOMP(high) VCOMP_ZCT TTMSD From disabled state, release COMP/EN pin to enable device (2.75 V VREG 5.5 V) (2.75 V VREG 5.5 V) (2.75 V VREG 5.5 V) Rising temperature 0.47 2.55 1.07 155 15 6 V V C C ms The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 60 and Figure 61), CGATE = 4.3 nF, and the upper- and lower-side MOSFETs being Infineon BSC042N03MSG. 2 Not automatic test equipment (ATE) tested. Rev. 0 | Page 4 of 44 ADP1870/ADP1871 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VREG to PGND, GND VIN to PGND FB, COMP/EN to GND DRVL to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND JA (10-Lead MSOP) 2-Layer Board 4-Layer Board Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) Rating -0.3 V to +6 V -0.3 V to +28 V -0.3 V to (VREG + 0.3 V) -0.3 V to (VREG + 0.3 V) -2.0 V to +28 V -0.6 V to (VREG + 0.3 V) -0.3 V to 28 V -0.3 V to VREG 0.3 V 213.1C/W 171.7C/W -40C to +125C -65C to +150C JEDEC J-STD-020 300C THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type JA (10-Lead MSOP) 2-Layer Board 4- Layer Board 1 JA1 213.1 171.7 Unit C/W C/W JA is specified for the worst-case conditions; that is, JA is specified for the device soldered in a circuit board for surface-mount packages. BOUNDARY CONDITION In determining the values given in Table 2 and Table 3, natural convection was used to transfer heat to a 4-layer evaluation board. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to PGND. Rev. 0 | Page 5 of 44 ADP1870/ADP1871 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 COMP/EN 2 FB 3 GND 4 VREG 5 10 BST SW DRVH 08730-003 ADP1870/ ADP1871 TOP VIEW (Not to Scale) 9 8 7 6 PGND DRVL Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VIN COMP/EN FB GND VREG DRVL PGND DRVH SW BST Description High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC. Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations section). Internal Regulator Supply Bias Voltage for the ADP1870/ADP1871 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 F directly from this pin to PGND and a 0.1 F across VREG and GND are recommended. Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see Figure 69). Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET. Drive Output for the External Upper-Side, N-Channel MOSFET. Switch Node Connection. Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for increased gate drive capability. Rev. 0 | Page 6 of 44 ADP1870/ADP1871 TYPICAL PERFORMANCE CHARACTERISTICS 100 95 90 85 VIN = 13V (PSM) 80 75 70 65 60 55 50 45 40 35 V = 16.5V (PSM) IN 30 25 20 15 10 5 0 10 100 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 VIN = 13V VIN = 13V (PSM) EFFICIENCY (%) VIN = 16.5V VIN = 13V TA = 25C VOUT = 0.8V fSW = 300kHz WURTH INDUCTOR: 744325072, L = 0.72H, DCR = 1.3m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 08730-104 EFFICIENCY (%) VIN = 16.5V TA = 25C VOUT = 0.8V fSW = 600kHz WURTH INDUCTOR: 744355147, L = 0.47H, DCR = 0.67m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100 1k LOAD CURRENT (mA) 10k 100k 08730-107 08730-109 08730-108 VIN = 16.5V (PSM) 1k LOAD CURRENT (mA) 10k 100k Figure 4. Efficiency--300 kHz, VOUT = 0.8 V Figure 7. Efficiency--600 kHz, VOUT = 0.8 V 08730-105 100 95 VIN = 5V (PSM) 90 85 80 75 70 VIN = 16.5V 65 VIN = 13V (PSM) 60 55 VIN = 13V 50 45 40 VIN = 16.5V (PSM) 35 TA = 25C 30 VOUT = 1.8V 25 fSW = 300kHz 20 WURTH INDUCTOR: 15 744325120, L = 1.2H, DCR = 1.8m 10 INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER) 0 10 100 1k 10k 100k LOAD CURRENT (mA) 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 VIN = 13V VIN = 13V (PSM) EFFICIENCY (%) EFFICIENCY (%) VIN = 16.5V (PSM) VIN = 16.5V TA = 25C VOUT = 1.8V fSW = 600kHz WURTH INDUCTOR: 744325072, L = 0.72H, DCR = 1.3m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100 1k LOAD CURRENT (mA) 10k 100k Figure 5. Efficiency--300 kHz, VOUT = 1.8 V Figure 8. Efficiency--600 kHz, VOUT = 1.8 V 1k LOAD CURRENT (mA) 10k 100k 08730-106 100 95 VIN = 16.5V (PSM) 90 85 80 75 V = 13V (PSM) IN 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 EFFICIENCY (%) VIN = 16.5V TA = 25C VOUT = 7V fSW = 300kHz WURTH INDUCTOR: 7443551200, L = 2.0H, DCR = 2.6m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) EFFICIENCY (%) VIN = 13V 100 VIN = 13V (PSM) 95 90 V = 16.5V (PSM) IN 85 80 75 70 65 VIN = 16.5V 60 55 50 VIN = 20V (PSM) VIN = 20V 45 40 35 TA = 25C 30 VOUT = 5V 25 fSW = 600kHz 20 WURTH INDUCTOR: 15 744318180, L = 1.4H, DCR = 3.2m 10 INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER) 0 10 100 1k 10k 100k LOAD CURRENT (mA) Figure 6. Efficiency--300 kHz, VOUT = 7 V Figure 9. Efficiency--600 kHz, VOUT = 5 V Rev. 0 | Page 7 of 44 ADP1870/ADP1871 100 95 90 85 80 75 70 65 VIN = 13V (PSM) 60 55 50 45 40 35 30 VIN = 16.5V (PSM) 25 20 15 10 5 0 10 100 0.807 VIN = 13V 0.806 0.805 0.804 OUTPUT VOLTAGE (V) 0.803 0.802 0.801 0.800 0.799 0.798 0.797 0.796 0.795 0.794 0.793 0.792 0 VIN = 13V +125C +25C -40C 2000 VIN = 16.5V +125C +25C -40C 4000 6000 8000 10,000 08730-013 EFFICIENCY (%) VIN = 16.5V TA = 25C VOUT = 0.8V fSW = 1.0MHz WURTH INDUCTOR: 744303012, L = 0.12H, DCR = 0.33m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 1k LOAD CURRENT (mA) 10k 100k 08730-110 LOAD CURRENT (mA) Figure 10. Efficiency--1.0 MHz, VOUT = 0.8 V Figure 13. Output Voltage Accuracy--300 kHz, VOUT = 0.8 V 1k 10k 100k 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 11. Efficiency--1.0 MHz, VOUT = 1.8 V Figure 14. Output Voltage Accuracy--300 kHz, VOUT = 1.8 V 100 1k LOAD CURRENT (mA) 10k 100k 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 LOAD CURRENT (mA) Figure 12. Efficiency--1.0 MHz, VOUT = 5 V Figure 15. Output Voltage Accuracy--300 kHz, VOUT = 7 V Rev. 0 | Page 8 of 44 08730-015 08730-112 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 VIN = 13V (PSM) VIN = 16.5V (PSM) VIN = 13V VIN = 16.5V TA = 25C VOUT = 5V fSW = 1.0MHz WURTH INDUCTOR: 744355090, L = 0.9H, DCR = 1.6m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 7.100 7.095 7.090 7.085 7.080 7.075 7.070 7.065 7.060 7.055 7.050 7.045 7.040 7.035 7.030 7.025 7.020 7.015 7.010 7.005 7.000 OUTPUT VOLTAGE (V) EFFICIENCY (%) +125C +25C -40C VIN = 13V VIN = 16.5V 08730-014 08730-111 100 95 90 85 80 VIN = 13V (PSM) 75 70 65 60 55 50 45 40 V = 16.5V (PSM) IN 35 30 25 20 15 10 5 0 10 100 1.821 VIN = 13V 1.816 OUTPUT VOLTAGE (V) 1.811 1.806 1.801 1.796 1.791 1.786 VIN = 5.5V +125C +25C -40C VIN = 13V +125C +25C -40C VIN = 16.5V +125C +25C -40C EFFICIENCY (%) VIN = 16.5V TA = 25C VOUT = 1.8V fSW = 1.0MHz WURTH INDUCTOR: 744303022, L = 0.22H, DCR = 0.33m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) ADP1870/ADP1871 0.808 0.806 0.804 FREQUENCY (kHz) 0.807 0.805 0.803 OUTPUT VOLTAGE (V) 0.801 0.799 0.797 0.795 0.793 0.791 VIN = 13V +125C +25C -40C 0 2000 4000 VIN = 16.5V +125C +25C -40C 6000 8000 10,000 08730-118 08730-020 08730-019 0.802 0.800 0.798 0.796 0.794 0.792 0 +125C +25C -40C VIN = 13V VIN = 16.5V 08730-115 0.789 0.787 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 16. Output Voltage Accuracy--600 kHz, VOUT = 0.8 V Figure 19. Output Voltage Accuracy--1.0 MHz, VOUT = 0.8 V 08730-016 1.818 1.816 1.814 1.812 1.810 1.808 1.806 1.804 1.802 1.800 1.798 1.796 1.794 1.792 1.790 1.788 1.786 1.784 1.782 1.780 1.778 1.776 1.774 1.772 1.770 0 1500 3000 1.820 1.815 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.810 1.805 1.800 VIN = 13V +125C +25C -40C 4500 6000 VIN = 16.5V +125C +25C -40C 7500 9000 10,500 12,000 1.795 VIN = 13V +125C +25C -40C 0 VIN = 16.5V +125C +25C -40C 1.790 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 17. Output Voltage Accuracy--600 kHz, VOUT = 1.8 V Figure 20. Output Voltage Accuracy--1.0 MHz, VOUT = 1.8 V 5.030 5.025 5.020 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 5.04 5.03 5.02 5.01 5.00 4.99 4.98 4.97 4.96 4.95 4.94 4.93 +125C +25C -40C 0 VIN = 13V VIN = 16.5V VIN = 20V 08730-017 5.015 5.010 5.005 5.000 4.995 4.990 4.985 4.980 4.975 4.970 4.92 4.91 4.90 0 VIN = 13V +125C +25C -40C VIN = 16.5V +125C +25C -40C 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 18. Output Voltage Accuracy--600 kHz, VOUT = 5 V Figure 21. Output Voltage Accuracy--1.0 MHz, VOUT =5 V Rev. 0 | Page 9 of 44 ADP1870/ADP1871 601.0 600.5 FEEDBACK VOLTAGE (V) 900 880 +125C +25C -40C 600.0 599.5 VREG = 5V, VIN = 13V 599.0 598.5 598.0 597.5 597.0 -40.0 SWITCHING FREQUENCY (kHz) 08730-121 VREG = 5V, VIN = 30V 860 840 820 800 780 760 740 720 -7.5 25.0 57.5 90.0 122.5 13.5 14.0 14.5 15.0 15.5 16.0 16.5 TEMPERATURE (C) VIN (V) Figure 22. Feedback Voltage vs. Temperature Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, VIN Range = 13 V to 16.5 V 325 315 SWITCHING FREQUENCY (kHz) +125C +25C -40C NO LOAD 280 265 VIN = 13V VIN = 20V VIN = 16.5V +125C +25C -40C 305 FREQUENCY (kHz) 250 295 285 275 265 255 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 VIN (V) 235 220 205 08730-022 0 2000 4000 6000 8000 10,000 LOAD CURRENT (mA) Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, 10% of 12 V Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V 650 +125C +25C -40C NO LOAD 330 320 310 VIN = 20V VIN = 13V VIN = 16.5V +125C +25C -40C SWITCHING FREQUENCY (kHz) 600 FREQUENCY (kHz) 300 290 280 270 260 250 08730-026 550 500 450 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16.2 08730-123 400 13.0 240 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,00 VIN (V) LOAD CURRENT (mA) Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V, VIN Range = 13 V to 16.5 V Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V Rev. 0 | Page 10 of 44 08730-025 190 08730-124 700 13.0 ADP1870/ADP1871 338 334 330 FREQUENCY (kHz) FREQUENCY (kHz) VIN = 13V VIN = 16.5V +125C +25C -40C 326 322 318 314 310 306 302 08730-027 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 LOAD CURRENT (mA) 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 28. Frequency vs. Load Current, 300 kHz, VOUT = 7 V Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V 540 510 480 FREQUENCY (kHz) VIN = 13V VIN = 16.5V +125C +25C -40C 850 VIN = 13V VIN = 16.5V +125C +25C -40C 775 FREQUENCY (kHz) 700 450 420 390 360 330 300 0 1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000 625 550 475 08730-028 0 2000 4000 6000 8000 10,000 12,000 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V Figure 32. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V 675 655 635 FREQUENCY (kHz) 1225 VIN = 13V VIN = 16.5V 1150 1075 FREQUENCY (kHz) VIN = 13V VIN = 16.5V +125C +25C -40C 615 595 575 555 535 515 495 0 LOAD CURRENT (mA) +125C +25C -40C 08730-029 1000 925 850 775 700 625 08730-032 550 0 1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) Figure 30. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V Rev. 0 | Page 11 of 44 08730-031 400 08730-030 298 740 733 726 719 712 705 698 691 684 677 670 663 656 649 642 635 628 621 VIN = 13V VIN = 16.5V +125C +25C -40C ADP1870/ADP1871 1450 1400 1350 FREQUENCY (kHz) 82 VIN = 13V VIN = 16.5V +125C +25C -40C MAXIMUM DUTY CYCLE (%) 80 78 76 74 72 70 68 66 64 08730-033 +125C +25C -40C 1300 1250 1200 1150 1100 1050 1000 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 LOAD CURRENT (mA) 6.7 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3 VIN (V) Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN) 2.658 2.657 2.656 MINUMUM OFF-TIME (ns) 680 630 580 530 480 430 380 330 280 230 08730-034 VREG = 2.7V VREG = 3.6V VREG = 5.5V 2.655 UVLO (V) 2.654 2.653 2.652 2.651 2.650 2.649 -40 -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) Figure 35. UVLO vs. Temperature Figure 38. Minimum Off-Time vs. Temperature 95 90 MAXIMUM DUTY CYCLE (%) 680 +125C +25C -40C MINUMUM OFF-TIME (ns) 630 580 +125C +25C -40C 85 80 75 70 65 60 55 300 530 480 430 380 330 280 230 08730-035 400 500 600 700 800 900 1000 3.1 3.5 3.9 4.3 4.7 5.1 5.5 FREQUENCY (kHz) VREG (V) Figure 36. Maximum Duty Cycle vs. Frequency Figure 39. Minimum Off-Time vs. VREG (Low Input Voltage) Rev. 0 | Page 12 of 44 08730-038 180 2.7 08730-037 180 -40 08730-036 62 5.5 ADP1870/ADP1871 800 720 640 RECTIFIER DROP (mV) BODY DIODE CONDUCTION TIME (ns) VREG = 2.7V VREG = 3.6V VREG = 5.5V +125C +25C -40C 80 72 64 56 48 40 32 24 16 8 2.7 300kHz 1MHz +125C +25C -40C 560 480 400 320 240 160 08730-039 400 500 600 700 800 900 1000 3.1 3.5 3.9 4.3 4.7 5.1 5.5 FREQUENCY (kHz) VREG (V) Figure 40. Internal Rectifier Drop vs. Frequency Figure 43. Lower-Side MOSFET Body Diode Conduction Time vs. VREG 1280 1200 1120 1040 RECTIFIER DROP (mV) VIN = 5.5V VIN = 13V VIN = 16.5V 1MHz 300kHz TA = 25C OUTPUT VOLTAGE 1 960 880 800 720 640 560 480 400 320 240 160 3.1 3.5 3.9 4.3 4.7 5.1 5.5 08730-040 INDUCTOR CURRENT 2 SW NODE 3 LOW SIDE 4 VREG (V) CH1 50mV BW CH3 10V BW CH2 5A CH4 5V M400ns T 35.8% A CH2 3.90A Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage) Over VIN Variation Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA 720 640 560 480 400 320 240 160 300kHz 1MHz +125C +25C -40C 1 OUTPUT VOLTAGE RECTIFIER DROP (mV) INDUCTOR CURRENT 2 SW NODE 3 LOW SIDE 4 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VREG (V) Figure 42. Internal Boost Rectifier Drop vs. VREG 08730-041 CH1 50mV BW CH3 10V BW CH2 5A CH4 5V M4.0s T 35.8% A CH2 3.90A Figure 45. PSM Waveform at Light Load, 500 mA Rev. 0 | Page 13 of 44 08730-044 80 2.7 08730-043 80 2.7 08730-042 80 300 ADP1870/ADP1871 OUTPUT VOLTAGE 4 2 OUTPUT VOLTAGE INDUCTOR CURRENT 12A NEGATIVE STEP 1 SW NODE 1 3 SW NODE 3 4 LOW SIDE CH1 5A CH3 10V 08730-045 CH4 100mV B W M400ns T 30.6% A CH3 2.20V CH1 10A CH3 20V CH2 200mV CH4 5V B W M20s A CH1 3.40A T 48.2% Figure 46. CCM Operation at Heavy Load, 12 A (See Figure 93 for Application Circuit) Figure 49. Negative Step During Heavy Load Transient Behavior--PSM Enabled, 12 A (See Figure 93 Application Circuit) OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE 12A STEP 1 12A STEP 1 LOW SIDE SW NODE 3 2 SW NODE LOW SIDE 4 08730-046 3 CH1 10A CH3 20V CH2 200mV CH4 5V B W M2ms T 75.6% A CH1 3.40A CH1 10A CH3 20V CH2 5V CH4 200mV B W M2ms T 15.6% A CH1 6.20A Figure 47. Load Transient Step--PSM Enabled, 12 A (See Figure 93 Application Circuit) Figure 50. Load Transient Step--Forced PWM at Light Load, 12 A (See Figure 93 Application Circuit) OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE 12A POSITIVE STEP 12A POSITIVE STEP 1 SW NODE 1 LOW SIDE 3 2 SW NODE LOW SIDE 4 08730-047 3 CH1 10A CH3 20V CH2 200mV CH4 5V B W M20s A CH1 3.40A T 30.6% CH1 10A CH3 20V CH2 5V CH4 200mV M20s B W T 43.8% A CH1 6.20A Figure 48. Positive Step During Heavy Load Transient Behavior--PSM Enabled, 12 A, VOUT = 1.8 V (See Figure 93 Application Circuit) Figure 51. Positive Step During Heavy Load Transient Behavior--Forced PWM at Light Load, 12 A, VOUT = 1.8 V (See Figure 93 Application Circuit) Rev. 0 | Page 14 of 44 08730-050 08730-049 08730-048 ADP1870/ADP1871 2 OUTPUT VOLTAGE 1 OUTPUT VOLTAGE INDUCTOR CURRENT 12A NEGATIVE STEP 1 2 SW NODE LOW SIDE 4 3 08730-051 CH1 10A CH3 20V CH2 200mV CH4 5V B W M10s A CH1 5.60A T 23.8% CH1 2V BW CH2 5A CH3 10V CH4 5V M2ms T 32.8% A CH1 720mV Figure 52. Negative Step During Heavy Load Transient Behavior--Forced PWM at Light Load, 12 A (See Figure 93 Application Circuit) Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz (See Figure 93 Application Circuit) OUTPUT VOLTAGE 1 1 OUTPUT VOLTAGE INDUCTOR CURRENT 2 LOW SIDE 4 INDUCTOR CURRENT 2 LOW SIDE 4 SW NODE 3 08730-052 SW NODE 3 CH1 2V BW CH2 5A CH3 10V CH4 5V M4ms T 49.4% A CH1 920mV CH1 2V BW CH2 5A CH3 10V CH4 5V M4ms T 41.6% A CH1 720mV Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode Figure 56. Power-Down Waveform During Heavy Load 1 OUTPUT VOLTAGE 1 OUTPUT VOLTAGE INDUCTOR CURRENT INDUCTOR CURRENT 2 2 SW NODE SW NODE 3 3 LOW SIDE LOW SIDE 4 08730-053 4 CH1 5V BW CH3 10V CH2 10A CH4 5V M10s T 36.2% A CH2 8.20A CH1 50mV BW CH3 10V BW CH2 5A CH4 5V M2s T 35.8% A CH2 3.90A Figure 54. Magnified Waveform During Hiccup Mode Figure 57. Output Voltage Ripple Waveform During PSM Operation at Light Load, 2 A Rev. 0 | Page 15 of 44 08730-056 08730-055 08730-054 4 LOW SIDE SW NODE 3 ADP1870/ADP1871 18ns (tr,DRVL ) LOW SIDE OUTPUT VOLTAGE 1 4 HIGH SIDE 24ns (tpdh,DRVL ) LOW SIDE 4 HS MINUS SW SW NODE 3 3 2 11ns (tf,DRVH ) SW NODE INDUCTOR CURRENT 2 08730-057 M TA = 25C 08730-060 08730-062 08730-061 CH1 1V BW CH3 10V BW CH2 5A CH4 2V M1ms T 63.2% A CH1 1.56V CH2 5V CH3 5V CH4 2V MATH 2V 20ns M20ns T 39.2% A CH2 4.20V Figure 58. Soft Start and RES Detect Waveform Figure 61. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms (CIN = 4.3 nF (Upper-/Lower-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)) LOW SIDE TA = 25C 570 550 530 510 490 470 450 VREG = 5.5V VREG = 3.6V VREG = 2.7V 4 HIGH SIDE SW NODE 3 2 M HS MINUS SW CH3 5V MATH 2V 40ns 08730-058 TRANSCONDUCTANCE (S) CH2 5V CH4 2V M40ns T 29.0% A CH2 4.20V 430 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 59. Output Drivers and SW Node Waveforms Figure 62. Transconductance (Gm) vs. Temperature LOW SIDE 16ns (tf,DRVL ) TA = 25C 680 630 TRANSCONDUCTANCE (S) +125C +25C -40C 580 530 480 430 380 330 2.7 4 22ns (tpdhDRVH ) HIGH SIDE 25ns (tr,DRVH) SW NODE 3 2 M HS MINUS SW 08730-059 CH2 5V CH3 5V CH4 2V MATH 2V 40ns M40ns T 29.0% A CH2 4.20V 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 VREG (V) Figure 60. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms (CIN = 4.3 nF (Upper-/Lower-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)) Rev. 0 | Page 16 of 44 Figure 63. Transconductance (Gm) vs. VREG ADP1870/ADP1871 1.30 1.25 1.20 QUIESCENT CURRENT (mA) 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 3.1 3.5 3.9 4.3 4.7 5.1 5.5 08730-163 +125C +25C -40C 0.70 2.7 VREG (V) Figure 64. Quiescent Current vs. VREG Rev. 0 | Page 17 of 44 ADP1870/ADP1871 ADP1870/ADP1871 BLOCK DIAGRAM ADP1870/ADP1871 tON TIMER C PRECISION ENABLE BLOCK TO ENABLE ALL BLOCKS LDO SW INFORMATION R (TRIMMED) I VREG VIN VREG tON = 2RC(VOUT/VIN) REF SW FILTER VREG BIAS BLOCK AND REFERENCE REF_ZERO ISS SS COMP CSS COMP/ EN FB SS_REF ERROR AMP INL_HICC PSM STATE MACHINE TON BG_REF BG_REF BG_REF 300k HI SW 8k BG_REF BG_REF 0.6V PWM IREV COMP LOWER COMP CLAMP REF_ZERO CS GAIN SET 0.4V CS AMP LO LS VREG DRVL PGND LEVEL SHIFT HS SW DRVH BST ADC RES DETECT AND GAIN SET GND Figure 65. ADP1870/ADP1871 Block Diagram Rev. 0 | Page 18 of 44 08730-063 ADP1870/ADP1871 THEORY OF OPERATION The ADP1870/ADP1871 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by utilizing valley current-mode control architecture. This allows the ADP1870/ ADP1871 to drive all N-channel power stages to regulate output voltages as low as 0.6 V. ADP1870/ADP1871, reducing the supply current of the devices to approximately 140 A. For more information, see Figure 67. ADP1870/ADP1871 FB VREG SS ERROR AMPLIFIER PRECISION ENABLE TO ENABLE ALL BLOCKS 285mV 0.6V COMP/EN CC RC CC2 STARTUP The ADP1870/ADP1871 have an internal regulator (VREG) for biasing and supplying power for the integrated MOSFET drivers. A bypass capacitor should be located directly across the VREG (Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence is the biasing of the current-sense amplifier, the current-sense gain circuit (see the Programming Resistor (RES) Detect Circuit section), the soft start circuit, and the error amplifier. The current-sense blocks provide valley current information (see the Programming Resistor (RES) Detect Circuit section) and are a variable of the compensation equation for loop stability (see the Compensation Network section). The valley current information is extracted by forcing 0.4 V across the DRVL output and PGND pin, which generates a current depending on the resistor across DRVL and PGND in a process performed by the RES detect circuit. The current through the resistor is used to set the current-sense amplifier gain. This process takes approximately 800 s, after which the drive signal pulses appear at the DRVL and DRVH pins synchronously and the output voltage begins to rise in a controlled manner through the soft start sequence. The rise time of the output voltage is determined by the soft start and error amplifier blocks (see the Soft Start section). At the beginning of a soft start, the error amplifier charges the external compensation capacitor, causing the COMP/EN pin to rise above the enable threshold of 285 mV, thus enabling the ADP1870/ADP1871. Figure 66. Release COMP/EN Pin to Enable the ADP1870/ADP1871 COMP/EN >2.4V 2.4V HICCUP MODE INITIALIZED MAXIMUM CURRENT (UPPER CLAMP) 1.0V ZERO CURRENT USABLE RANGE ONLY AFTER SOFT START PERIOD IF CONTUNUOUS CONDUCTION MODE OF OPERATION IS SELECTED. 500mV LOWER CLAMP 0V 35mV HYSTERESIS Figure 67. COMP/EN Voltage Range UNDERVOLTAGE LOCKOUT The undervoltage lockout (UVLO) feature prevents the part from operating both the upper- and lower-side MOSFETs at extremely low or undefined input voltage (VIN) ranges. Operation at an undefined bias voltage may result in the incorrect propagation of signals to the high-side power switches. This, in turn, results in invalid output behavior that can cause damage to the output devices, ultimately destroying the device tied at the output. The UVLO level has been set at 2.65 V (nominal). SOFT START The ADP1870/ADP1871 have digital soft start circuitry, which involves a counter that initiates an incremental increase in current, by 1 A, via a current source on every cycle through a fixed internal capacitor. The output tracks the ramping voltage by producing PWM output pulses to the upper-side MOSFET. The purpose is to limit the in-rush current from the high voltage input supply (VIN) to the output (VOUT). ON-BOARD LOW DROPOUT REGULATOR The ADP1870 uses an on-board LDO to bias the internal digital and analog circuitry. With proper bypass capacitors connected to the VREG pin (output of internal LDO), this pin also provides power for the internal MOSFET drivers. It is recommended to float VREG if VIN is utilized for greater than 5.5 V operation. The minimum voltage where bias is guaranteed to operate is 2.75 V at VREG. For applications where VIN is decoupled from VREG, the minimum voltage at VIN must be 2.9 V. It is recommended that PRECISION ENABLE CIRCUITRY The ADP1870/ADP1871 employ precision enable circuitry. The enable threshold is 285 mV typical with 35 mV of hysteresis. The devices are enabled when the COMP/EN pin is released, allowing the error amplifier output to rise above the enable threshold (see Figure 66). Grounding this pin disables the Rev. 0 | Page 19 of 44 08730-065 285mV PRECISION ENABLE THRESHOLD 08730-064 ADP1870/ADP1871 VIN and VREG be tied together if the VIN pin is subjected to a 2.75 V rail. Table 5. Power Input and LDO Output Configurations VIN >5.5 V <5.5 V VREG Float Connect to VIN Comments Must use the LDO LDO drop voltage is not realized (that is, if VIN = 2.75 V, then VREG = 2.75 V) LDO drop is realized LDO drop is realized, minimum VIN recommendation is 2.95 V CS GAIN SET ADC 0.4V CS AMP SW PGND DRVL <5.5 V Ranges above and below 5.5 V Float Float RES Figure 69. RES Detect Circuit for Current-Sense Gain Programming Table 6. Current-Sense Gain Programming Resistor 47 k 22 k Open 100 k ACS 3 V/V 6 V/V 12 V/V 24 V/V THERMAL SHUTDOWN The thermal shutdown is a self-protection feature to prevent the IC from damage due to a very high operating junction temperature. If the junction temperature of the device exceeds 155C, the part enters the thermal shutdown state. In this state, the device shuts off both the upper- and lower-side MOSFETs and disables the entire controller immediately, thus reducing the power consumption of the IC. The part resumes operation after the junction temperature of the part cools to less than 140C. VALLEY CURRENT-LIMIT SETTING The architecture of the ADP1870/ADP1871 is based on valley current-mode control. The current limit is determined by three components: the RON of the lower-side MOSFET, the error amplifier output voltage swing (COMP), and the current-sense gain. The COMP range is internally fixed at 1.4 V. The current-sense gain is programmable via an external resistor at the DRVL pin (see the Programming Resistor (RES) Detect Circuit section). The RON of the lower-side MOSFET can vary over temperature and usually has a positive TC (meaning that it increases with temperature); therefore, it is recommended to program the current-sense gain resistor based on the rated RON of the MOSFET at 125C. Because the ADP1870/ADP1871 are based on valley current control, the relationship between ICLIM and ILOAD is as follows: PROGRAMMING RESISTOR (RES) DETECT CIRCUIT Upon startup, one of the first blocks to become active is the RES detect circuit. This block powers up before soft start begins. It forces a 0.4 V reference value at the DRVL output (see Figure 68) and is programmed to identify four possible resistor values: 47 k, 22 k, open, and 100 k. The RES detect circuit digitizes the value of the resistor at the DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code that is used to program four separate gain configurations in the current-sense amplifier (see Figure 69). Each configuration corresponds to a current-sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V, 24 V/V, respectively (see Table 6 and Table 7). This variable is used for the valley current-limit setting, which sets up the appropriate current-sense gain for a given application and sets the compensation necessary to achieve loop stability (see the Valley Current-Limit Setting and Compensation Network sections). ADP1870/ ADP1871 Q1 DRVH SW Q2 DRVL CS GAIN PROGRAMMING 08730-066 K I CLIM = I LOAD x 1 - I 2 where: KI is the ratio between the inductor ripple current and the desired average load current (see Figure 70). ICLIM is the desired valley current limit. ILOAD is the current load. Establishing KI helps to determine the inductor value (see the Inductor Selection section), but in most cases KI = 0.33. RRES RIPPLE CURRENT = LOAD CURRENT ILOAD 3 Figure 68. Programming Resistor Location 08730-068 VALLEY CURRENT LIMIT Figure 70. Valley Current Limit to Average Current Relation Rev. 0 | Page 20 of 44 08730-067 ADP1870/ADP1871 When the desired valley current limit (ICLIM) has been determined, the current-sense gain can be calculated as follows: I CLIM = 1.4 V ACS x RON The valley current limit is programmed as outlined in Table 7 and Figure 71. The inductor chosen must be rated to handle the peak current, which is equal to the valley current from Table 7 plus the peak-to-peak inductor ripple current (see the Inductor Selection section). In addition, the peak current value must be used to compute the worst-case power dissipation in the MOSFETs (see Figure 72). 49A where: RON is the channel impedance of the lower-side MOSFET. ACS is the current-sense gain multiplier (see Table 6 and Table 7). Although the ADP1870/ADP1871 have only four discrete currentsense gain settings for a given RON variable, Table 7 and Figure 71 outline several available options for the valley current setpoint based on various RON values. Table 7. Valley Current Limit Program1 RON (m) 1.5 2 2.5 3 3.5 4.5 5 5.5 10 15 18 1 MAXIMUM DC LOAD CURRENT 39.5A INDUCTOR CURRENT I = 65% OF 37A 35A I = 45% 32.25A OF 32.25A 30A 37A COMP OUTPUT 47 k ACS = 3 V/V Valley Current Level 22 k Open ACS = 6 V/V ACS = 12 V/V I = 33% OF 30A 31.0 26.0 23.3 15.5 13.0 39.0 33.4 26.0 23.4 21.25 11.7 7.75 6.5 100 k ACS = 24 V/V 38.9 29.2 23.3 19.5 16.7 13 11.7 10.6 5.83 7.5 3.25 2.4V VALLEY CURRENT-LIMIT THRESHOLD (SET FOR 25A) COMP OUTPUT SWING 0A 1V Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current HICCUP MODE DURING SHORT CIRCUIT A current-limit violation occurs when the current across the source and drain of the lower-side MOSFET exceeds the current-limit setpoint. When 32 current-limit violations are detected, the controller enters idle mode and turns off the MOSFETs for 6 ms, allowing the converter to cool down. Then, the controller reestablishes soft start and begins to cause the output to ramp up again (see Figure 73). While the output ramps up, COMP is monitored to determine if the violation is still present. If it is still present, the idle event occurs again, followed by the full-chip power-down sequence. This cycle continues until the violation no longer exists. If the violation disappears, the converter is allowed to switch normally, maintaining regulation. Refer to Figure 71 for more information and a graphical representation. 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 VALLEY CURRENT LIMIT (A) RES = 47k ACS = 3V/V RES = NO RES ACS = 12V/V RES = 22k ACS = 6V/V RES = 100k ACS = 24V/V 08730-069 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RON (m) Figure 71. Valley Current-Limit Value vs. RON of the Lower-Side MOSFET for Each Programming Resistor (RES) REPEATED CURRENT-LIMIT VIOLATION DETECTED HS A PREDETERMINED NUMBER SOFT START IS OF PULSES IS COUNTED TO REINITIALIZED TO ALLOW THE CONVERTER MONITOR IF THE TO COOL DOWN VIOLATION STILL EXISTS CLIM ZERO CURRENT Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation Rev. 0 | Page 21 of 44 08730-071 08730-070 ADP1870/ADP1871 SYNCHRONOUS RECTIFIER The ADP1870/ADP1871 employ an internal lower-side MOSFET driver to drive the external upper- and lower-side MOSFETs. The synchronous rectifier not only improves overall conduction efficiency, but also ensures proper charging to the bootstrap capacitor located at the upper-side driver input. This is beneficial during startup to provide sufficient drive signal to the external upper-side MOSFET and to attain fast turn-on response, which is essential for minimizing switching losses. The integrated upperand lower-side MOSFET drivers operate in complementary fashion with built-in anticross conduction circuitry to prevent unwanted shoot-through current that may potentially damage the MOSFETs or reduce efficiency as a result of excessive power loss. As soon as the forward current through the lower-side MOSFET decreases to a level where 10 mV = IQ2 x RON(Q2) the zero-cross comparator (or IREV comparator) emits a signal to turn off the lower-side MOSFET. From this point, the slope of the inductor current ramping down becomes steeper (see Figure 76) as the body diode of the lower-side MOSFET begins to conduct current and continues conducting current until the remaining energy stored in the inductor has been depleted. ANOTHER tON EDGE IS TRIGGERED WHEN VOUT FALLS BELOW REGULATION SW tON POWER SAVING MODE (PSM) VERSION (ADP1871) The power saving mode version of the ADP1870 is the ADP1871. The ADP1871 operates in the discontinuous conduction mode (DCM) and pulse skips at light load to mid load currents. It outputs pulses as necessary to maintain output regulation. Unlike the continuous conduction mode (CCM), DCM operation prevents negative current, thus allowing improved system efficiency at light loads. Current in the reverse direction through this pathway, however, results in power dissipation and therefore a decrease in efficiency. HS LS HS AND LS IN IDLE MODE ILOAD ZERO-CROSS COMPARATOR DETECTS 10mV OFFSET AND TURNS OFF LS 0A 10mV = RON x ILOAD tON Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current LS HS AND LS ARE OFF OR IN IDLE MODE tOFF The system remains in idle mode until the output voltage drops below regulation. A PWM pulse is then produced, turning on the upper-side MOSFET to maintain system regulation. The ADP1871 does not have an internal clock, so it switches purely as a hysteretic controller as described in this section. TIMER OPERATION AS THE INDUCTOR CURRENT APPROACHES ZERO CURRENT, THE STATE MACHINE TURNS OFF THE LOWER-SIDE MOSFET. 08730-072 ILOAD 0A Figure 74. Discontinuous Mode of Operation (DCM) To minimize the chance of negative inductor current buildup, an on-board zero-cross comparator turns off all upper- and lower-side switching activities when the inductor current approaches the zero current line, causing the system to enter idle mode, where the upper- and lower-side MOSFETs are turned off. To ensure idle mode entry, a 10 mV offset, connected in series at the SW node, is implemented (see Figure 75). ZERO-CROSS COMPARATOR SW IQ2 10mV The ADP1870/ADP1871 employ a constant on-time architecture, which provides a variety of benefits, including improved load and line transient response when compared with a constant (fixed) frequency current-mode control loop of comparable loop design. The constant on-time timer, or tON timer, senses the high input voltage (VIN) and the output voltage (VOUT) using SW waveform information to produce an adjustable one-shot PWM pulse that varies the on-time of the upper-side MOSFET in response to dynamic changes in input voltage, output voltage, and load current conditions to maintain regulation. It then generates an on-time (tON) pulse that is inversely proportional to VIN. t ON = K x VOUT VIN where: K is a constant that is trimmed using an RC timer product for the 300 kHz, 600 kHz, and 1.0 MHz frequency options. 08730-073 LS Q2 Figure 75. Zero-Cross Comparator with 10 mV of Offset Rev. 0 | Page 22 of 44 08730-074 ADP1870/ADP1871 tON C I SW INFORMATION R (TRIMMED) 08730-075 VREG VIN To illustrate this feature more clearly, this section describes one such load transient event--a positive load step--in detail. During load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off-time (DRVL on-time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. When a positive load step occurs, the error amplifier (out of phase of the output, VOUT) produces new voltage information at its output (COMP). In addition, the current-sense amplifier senses new inductor current information during this positive load transient event. The error amplifier's output voltage reaction is compared with the new inductor current information that sets the start of the next switching cycle. Because current information is produced from valley current sensing, it is sensed at the down ramp of the inductor current, whereas the voltage loop information is sensed through the counter action upswing of the error amplifier's output (COMP). The result is a convergence of these two signals (see Figure 78), which allows an instantaneous increase in switching frequency during the positive load transient event. In summary, a positive load step causes VOUT to transient down, which causes COMP to transient up and therefore shortens the off-time. This resulting increase in frequency during a positive load transient helps to quickly bring VOUT back up in value and within the regulation window. Similarly, a negative load step causes the off-time to lengthen in response to VOUT rising. This effectively increases the inductor demagnetizing phase, helping to bring VOUT within regulation. In this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery. Because the ADP1870/ADP1871 has the ability to respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed-frequency equivalent. Therefore, using a pseudo-fixed frequency results in significantly better load transient performance than using a fixed frequency. Figure 77. Constant On-Time Time The constant on-time (tON) is not strictly "constant" because it varies with VIN and VOUT. However, this variation occurs in such a way as to keep the switching frequency virtually independent of VIN and VOUT. The tON timer uses a feedforward technique, applied to the constant on-time control loop, making it a pseudo-fixed frequency to a first order. Second-order effects, such as dc losses in the external power MOSFETs (see the Efficiency Consideration section), cause some variation in frequency vs. load current and line voltage. These effects are shown in Figure 23 to Figure 34. The variations in frequency are much reduced compared with the variations generated when the feedforward technique is not utilized. The feedforward technique establishes the following relationship: f SW = 1 K where fSW is the controller switching frequency (300 kHz, 600 kHz, and 1.0 MHz). The tON timer senses VIN and VOUT to minimize frequency variation as previously explained. This provides a pseudo-fixed frequency as explained in the Pseudo-Fixed Frequency section. To allow headroom for VIN and VOUT sensing, adhere to the following equations: VREG VIN/8 + 1.5 VREG VOUT/4 For typical applications where VREG is 5 V, these equations are not relevant; however, for lower VREG inputs, care may be required. PSEUDO-FIXED FREQUENCY The ADP1870/ADP1871 employ a constant on-time control scheme. During steady state operation, the switching frequency stays relatively constant, or pseudo-fixed. This is due to the oneshot tON timer that produces a high-side PWM pulse with a "fixed" duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state. During load transients, the frequency momentarily changes for the duration of the transient event so that the output comes back within regulation more quickly than if the frequency were fixed or if it were to remain unchanged. After the transient event is complete, the frequency returns to a pseudo-fixed frequency value to a first order. LOAD CURRENT DEMAND CS AMP OUTPUT ERROR AMP OUTPUT VALLEY TRIP POINTS PWM OUTPUT fSW >fSW 08730-076 Figure 78. Load Transient Response Operation Rev. 0 | Page 23 of 44 ADP1870/ADP1871 APPLICATIONS INFORMATION FEEDBACK RESISTOR DIVIDER The required resistor divider network can be determined for a given VOUT value because the internal band gap reference (VREF) is fixed at 0.6 V. Selecting values for RT and RB determines the minimum output load current of the converter. Therefore, for a given value of RB, the RT value can be determined through the following expression: RT = R B x (VOUT - 0.6 V) 0.6 V Table 8. Recommended Inductors L (H) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 DCR (m) 0.33 0.33 0.67 1.3 1.6 1.8 3.3 3.2 2.6 2.5 ISAT (A) 55 30 50 35 28 25 20 24 22 16.5 Dimensions (mm) 10.2 x 7 10.2 x 7 13.2 x 12.8 10.5 x 10.2 13 x 12.8 10.5 x 10.2 10.5 x 10.2 14 x 12.8 13.2 x 12.8 12.5 x 12.5 Manufacturer Wurth Elek. Wurth Elek. Wurth Elek. Wurth Elek. Wurth Elek. Wurth Elek. Wurth Elek. Wurth Elek. Wurth Elek. AIC Technology Model Number 744303012 744303022 744355147 744325072 744355090 744325120 7443552100 744318180 7443551200 CEP125U-R80 INDUCTOR SELECTION The inductor value is inversely proportional to the inductor ripple current. The peak-to-peak ripple current is given by I L = K I x I LOAD I LOAD 3 OUTPUT RIPPLE VOLTAGE (VRR) The output ripple voltage is the ac component of the dc output voltage during steady state. For a ripple error of 1.0%, the output capacitor value needed to achieve this tolerance can be determined using the following equation. (Note that an accuracy of 1.0% is possible only during steady state conditions, not during load transients.) VRR = (0.01) x VOUT where KI is typically 0.33. The equation for the inductor value is given by L= (V IN - VOUT ) VOUT x I L x f SW V IN where: VIN is the high voltage input. VOUT is the desired output voltage. fSW is the controller switching frequency (300 kHz, 600 kHz, and 1.0 MHz). When selecting the inductor, choose an inductor saturation rating that is above the peak current level, and then calculate the inductor current ripple (see the Valley Current-Limit Setting section and Figure 79). 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 8 10 12 14 16 18 20 I = 50% I = 40% OUTPUT CAPACITOR SELECTION The primary objective of the output capacitor is to facilitate the reduction of the output voltage ripple; however, the output capacitor also assists in the output voltage recovery during load transient events. For a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. The speed at which the output voltage settles during this recovery period depends on where the crossover frequency (loop bandwidth) is set. This crossover frequency is determined by the output capacitor, the equivalent series resistance (ESR) of the capacitor, and the compensation network. To calculate the small-signal voltage ripple (output ripple voltage) at the steady state operating point, use the following equation: 1 C OUT = I L x 8 x f x [V - (I L x ESR)] RIPPLE SW PEAK INDUCTOR CURRENT (A) I = 33% where ESR is the equivalent series resistance of the output capacitors. 22 24 26 28 30 08730-077 To calculate the output load step, use the following equation: VALLEY CURRENT LIMIT (A) Figure 79. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and 50% of Inductor Ripple Current COUT = 2 x f SW I LOAD x (VDROOP - (I LOAD x ESR)) where VDROOP is the amount that VOUT is allowed to deviate for a given positive load current step (ILOAD). Rev. 0 | Page 24 of 44 ADP1870/ADP1871 Ceramic capacitors are known to have low ESR. However, the trade-off of using X5R technology is that up to 80% of its capacitance might be lost due to derating as the voltage applied across the capacitor is increased (see Figure 80). Although X7R series capacitors can also be used, the available selection is limited to only up to 22 F. 20 10 X7R (50V) 0 Error Amplifier Output Impedance (ZCOMP) Assuming that CC2 is significantly smaller than CCOMP, CC2 can be omitted from the output impedance equation of the error amplifier. The transfer function simplifies to Z COMP = R COMP ( f CROSS + f ZERO ) f CROSS and fCROSS = 1 x f SW 12 CAPACITANCE CHARGE (%) -10 -20 -30 -40 -50 X5R (25V) -60 -70 X5R (16V) -80 -90 10F TDK 25V, X7R, 1210 C3225X7R1E106M 22F MURATA 25V, X7R, 1210 GRM32ER71E226KE15L 47F MURATA 16V, X5R, 1210 GRM32ER61C476KE15L 0 5 10 15 20 25 30 08730-078 where fZERO, the zero frequency, is set to be 1/4th of the crossover frequency for the ADP1870. Error Amplifier Gain (GM) The error amplifier gain (transconductance) is GM = 500 A/V Current-Sense Loop Gain (GCS) The current-sense loop gain is G CS = -100 DC VOLTAGE (VDC) Figure 80. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors 1 (A/V) ACS x RON Electrolytic capacitors satisfy the bulk capacitance requirements for most high current applications. Because the ESR of electrolytic capacitors is much higher than that of ceramic capacitors, when using electrolytic capacitors, several MLCCs should be mounted in parallel to reduce the overall series resistance. where: ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V (see the Programming Resistor (RES) Detect Circuit and Valley Current-Limit Setting sections). RON is the channel impedance of the lower-side MOSFET. COMPENSATION NETWORK Due to their current-mode architecture, the ADP1870/ADP1871 require Type II compensation. To determine the component values needed for compensation (resistance and capacitance values), it is necessary to examine the converter's overall loop gain (H) at the unity gain frequency (fSW/10) when H = 1 V/V: H = 1 V/V = G M x G CS x VOUT x Z COMP x Z FILT VREF Crossover Frequency The crossover frequency is the frequency at which the overall loop (system) gain is 0 dB (H = 1 V/V). For current-mode converters, such as the ADP1870, it is recommended that the user set the crossover frequency between 1/10th and 1/15th of the switching frequency. fCROSS = 1 f SW 12 Examining each variable at high frequency enables the unitygain transfer function to be simplified to provide expressions for the RCOMP and CCOMP component values. The relationship between CCOMP and fZERO (zero frequency) is as follows: f ZERO = 1 2 x R COMP x C COMP Output Filter Impedance (ZFILT) Examining the filter's transfer function at high frequencies simplifies to Z FILTER = ) The zero frequency is set to 1/4th of the crossover frequency. Combining all of the above parameters results in RCOMP = 2f CROSS C OUT VOUT f CROSS x x f CROSS + f ZERO G M GCS VREF 1 sC OUT at the crossover frequency (s = 2fCROSS). C COMP = 1 2 x x RCOMP x f ZERO Rev. 0 | Page 25 of 44 ADP1870/ADP1871 EFFICIENCY CONSIDERATIONS One of the important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents up to 20 A, the following are important MOSFET parameters that aid in the selection process: * * * * * 800 720 640 VREG = 2.7V VREG = 3.6V VREG = 5.5V RECTIFIER DROP (mV) 560 480 400 320 240 160 80 300 +125C +25C -40C 400 500 600 700 800 900 1000 08730-079 VGS (TH): the MOSFET support voltage applied between the gate and the source RDS (ON): the MOSFET on resistance during channel conduction QG: the total gate charge CN1: the input capacitance of the upper-side switch CN2: the input capacitance of the lower-side switch SWITCHING FREQUENCY (kHz) The following are the losses experienced through the external component during normal switching operation: * * * * * Figure 81. Internal Rectifier Voltage Drop vs. Switching Frequency Switching Loss The SW node transitions due to the switching activities of the upper- and lower-side MOSFETs. This causes removal and replenishing of charge to and from the gate oxide layer of the MOSFET, as well as to and from the parasitic capacitance associated with the gate oxide edge overlap and the drain and source terminals. The current that enters and exits these charge paths presents additional loss during these transition times. This loss can be approximately quantified by using the following equation, which represents the time in which charge enters and exits these capacitive regions: tSW-TRANS = RGATE x CTOTAL Channel conduction loss (both of the MOSFETs) MOSFET driver loss MOSFET switching loss Body diode conduction loss (lower-side MOSFET) Inductor loss (copper and core loss) Channel Conduction Loss During normal operation, the bulk of the loss in efficiency is due to the power dissipated through MOSFET channel conduction. Power loss through the upper-side MOSFET is directly proportional to the duty cycle (D) for each switching period, and the power loss through the lower-side MOSFET is directly proportional to 1 - D for each switching period. The selection of MOSFETs is governed by the amount of maximum dc load current that the converter is expected to deliver. In particular, the selection of the lower-side MOSFET is dictated by the maximum load current because a typical high current application employs duty cycles of less than 50%. Therefore, the lower-side MOSFET is in the on state for most of the switching period. 2 PN1,N2(CL) = D x R N1(ON) + (1 - D ) x R N2(ON) x I LOAD where: CTOTAL is the CGD + CGS of the external MOSFET. RGATE is the gate input resistance of the external MOSFET. The ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression: PSW ( LOSS) = t SW -TRANS t SW x I LOAD x V IN x 2 [ ] or PSW ( LOSS) = f SW x R GATE x C TOTAL x I LOAD x V IN x 2 MOSFET Driver Loss Other dissipative elements are the MOSFET drivers. The contributing factors are the dc current flowing through the driver during operation and the QGATE parameter of the external MOSFETs. [VREG x ( f SW ClowerFETVREG + I BIAS )] PDR ( LOSS ) = VDR x ( f SW CupperFETVDR + I BIAS ) + [ ] where: CupperFET is the input gate capacitance of the upper-side MOSFET. ClowerFET is the input gate capacitance of the lower-side MOSFET. IBIAS is the dc current flowing into the upper- and lower-side drivers. VDR is the driver bias voltage (that is, the low input voltage (VREG) minus the rectifier drop (see Figure 81)). VREG is the bias voltage. fSW is the controller switching frequency (300 kHz, 600 kHz, and 1.0 MHz) Rev. 0 | Page 26 of 44 ADP1870/ADP1871 Diode Conduction Loss The ADP1870/ADP1871 employ anticross conduction circuitry that prevents the upper- and lower-side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage. However, this blanking period comes with the trade-off of a diode conduction loss occurring immediately after the MOSFETs change states and continuing well into idle mode. The amount of loss through the body diode of the lower-side MOSFET during the antioverlap state is given by the following expression: PBODY ( LOSS) = t BODY ( LOSS) t SW x I LOAD x VF x 2 application to achieve minimal loss and negligible electromagnetic interference (EMI). 2 PDCR( LOSS) = DCR x I LOAD + Core Loss INPUT CAPACITOR SELECTION The goal in selecting an input capacitor is to reduce or minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for achieving predictable loop stability and transient performance. The problem with using bulk capacitors, other than their physical geometries, is their large equivalent series resistance (ESR) and large equivalent series inductance (ESL). Aluminum electrolytic capacitors have such high ESR that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies. If bulk capacitors are to be used, it is recommended that mulilayered ceramic capacitors (MLCC) be used in parallel due to their low ESR values. This dramatically reduces the input voltage ripple amplitude as long as the MLCCs are mounted directly across the drain of the upper-side MOSFET and the source terminal of the lower-side MOSFET (see the Layout Considerations section). Improper placement and mounting of these MLCCs may cancel their effectiveness due to stray inductance and an increase in trace impedance. I CIN ,rms = I LOAD,max x VOUT x (V IN - VOUT ) VOUT where: tBODY(LOSS) is the body conduction time (refer to Figure 82 for dead time periods). tSW is the period per switching cycle. VF is the forward drop of the body diode during conduction. (Refer to the selected external MOSFET data sheet for more information about the VF parameter.) 80 72 64 56 48 40 32 24 16 8 2.7 1MHz 300kHz +125C +25C -40C BODY DIODE CONDUCTION TIME (ns) 3.4 4.1 VREG (V) 4.8 5.5 08730-080 The maximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 - D while the upper-side MOSFET is in the off state. The input capacitor rms current reaches its maximum at Time D. When calculating the maximum input voltage ripple, account for the ESR of the input capacitor as follows: VRIPPLE,max = VRIPP + (ILOAD,max x ESR) Figure 82. Body Diode Conduction Time vs. Low Voltage Input (VREG) Inductor Loss During normal conduction mode, further power loss is caused by the conduction of current through the inductor windings, which have dc resistance (DCR). Typically, larger sized inductors have smaller DCR values. The inductor core loss is a result of the eddy currents generated within the core material. These eddy currents are induced by the changing flux, which is produced by the current flowing through the windings. The amount of inductor core loss depends on the core material, the flux swing, the frequency, and the core volume. Ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. It is recommended that shielded ferrite core material type inductors be used with the ADP1870/ADP1871 for a high current, dc-to-dc switching where: VRIPP is usually 1% of the minimum voltage input. ILOAD,max is the maximum load current. ESR is the equivalent series resistance rating of the input capacitor. Inserting VRIPPLE,max into the charge balance equation to calculate the minimum input capacitor requirement gives C IN,min = I LOAD,max VRIPPLE,max x D(1 - D) f SW or C IN,min = I LOAD,max 4 f SW VRIPPLE,max where D = 50%. Rev. 0 | Page 27 of 44 ADP1870/ADP1871 THERMAL CONSIDERATIONS The ADP1870/ADP1871 are used for dc-to-dc, step down, high current applications that have an on-board controller, an on-board LDO, and on-board MOSFET drivers. Because applications may require up to 20 A of load current delivery and be subjected to high ambient temperature surroundings, the selection of external upper- and lower-side MOSFETs must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125C. To avoid permanent or irreparable damage if the junction temperature reaches or exceeds 155C, the part enters thermal shutdown, turning off both external MOSFETs, and does not reenable until the junction temperature cools to 140C (see the On-Board Low Dropout Regulator section). In addition, it is important to consider the thermal impedance of the package. Because the ADP1870/ADP1871 employ an onboard LDO, the ac current (fxCxV) consumed by the internal drivers to drive the external MOSFETs adds another element of power dissipation across the internal LDO. Equation 3 shows the power dissipation calculations for the integrated drivers and for the internal LDO. Table 9 lists the thermal impedance for the ADP1870/ADP1871, which are available in a 10-lead MSOP. Table 9. Thermal Impedance for 10-lead MSOP Parameter 10-Lead MSOP JA 2-Layer Board 4-Layer Board Thermal Impedance 213.1C/W 171.7C/W The maximum junction temperature allowed for the ADP1870/ ADP1871 ICs is 125C. This means that the sum of the ambient temperature (TA) and the rise in package temperature (TR), which is caused by the thermal impedance of the package and the internal power dissipation, should not exceed 125C, as dictated by the following expression: TJ = TR x TA (1) where: TA is the ambient temperature. TJ is the maximum junction temperature. TR is the rise in package temperature due to the power dissipated from within. The rise in package temperature is directly proportional to its thermal impedance characteristics. The following equation represents this proportionality relationship: TR = JA x PDR(LOSS) (2) where: JA is the thermal resistance of the package from the junction to the outside surface of the die, where it meets the surrounding air. PDR(LOSS) is the overall power dissipated by the IC. The bulk of the power dissipated is due to the gate capacitance of the external MOSFETs and current running through the onboard LDO. The power loss equations for the MOSFET drivers and internal low dropout regulator (see the MOSFET Driver Loss section in the Efficiency Consideration section) are: PDR(LOSS) = [VDR x (fSWCupperFETVDR + IBIAS)] + [VREG x (fSWClowerFET VREG + IBIAS)] (3) Figure 83 specifies the maximum allowable ambient temperature that can surround the ADP1870/ADP1871 IC for a specified high input voltage (VIN). Figure 83 illustrates the temperature derating conditions for each available switching frequency for low, typical, and high output setpoints for the 10-lead MSOP package. All temperature derating criteria are based on a maximum IC junction temperature of 125C. 150 140 130 600kHz 300kHz 1MHz VOUT = 0.8V VOUT = 1.8V VOUT = HIGH SETPOINT where: CupperFET is the input gate capacitance of the upper-side MOSFET. ClowerFET is the input gate capacitance of the lower-side MOSFET. IBIAS is the dc current (2 mA) flowing into the upper- and lowerside drivers. VDR is the driver bias voltage (the low input voltage (VREG) minus the rectifier drop (see Figure 81)). VREG is the LDO output/bias voltage. PDISS ( LDO ) = PDR ( LOSS ) + (VIN - VREG ) x ( f SW x Ctotal x VREG + I BIAS ) MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (C) (4) 120 110 100 90 80 70 60 50 40 30 20 10 7.0 8.5 10.0 11.5 13.0 VIN (V) 14.5 16.0 17.5 19.0 08730-182 where: PDISS(LDO) is the power dissipated through the pass device in the LDO block across VIN and VREG. Ctotal is the CGD + CGS of the external MOSFET. VREG is the LDO output voltage and bias voltage. VIN is the high voltage input. IBIAS is the dc input bias current. PDR(LOSS) is the MOSFET driver loss. 0 5.5 Figure 83. Ambient Temperature vs. VIN for 10-Lead MSOP (171C/W), 4-Layer EVB, CIN = 4.3 nF (Upper-/Lower-Side MOSFET) Rev. 0 | Page 28 of 44 ADP1870/ADP1871 For example, if the external MOSFET characteristics are JA (10-lead MSOP) = 171.2C/W, fSW = 300 kHz, IBIAS = 2 mA, CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 4.62 V, and VREG = 5.0 V, then the power loss is P DR ( LOSS ) = V DR x f SW C upperFET V DR + I BIAS + [V REG x ( f SW C lowerFET V REG + I BIAS 3 -9 Inductor Determine inductor ripple current amplitude as follows: I LOAD =5A 3 VOUT V IN,MAX [ ( )] )] I L so calculating for the inductor value L= = (V IN,MAX - VOUT ) I L x f SW 3 = ( 4 . 62 x (300 x 10 x 3 . 3 x 10 x 4 .62 + 0 . 002 )) + (5 . 0 x (300 x 10 3 x 3 . 3 x 10 - 9 x 5 . 0 + 0 . 002 )) x = 57.12 mW PDISS( LDO ) = (V IN - VREG ) x ( f SW x C total x VREG + I BIAS ) (13.2 V - 1.8 V) = (13 V - 5 V) x (300 x 10 3 x 3.3 x 10 -9 x 5 + 0.002) = 55.6 mW PDISS(TOTAL ) = PDISS( LDO ) + PDR( LOSS ) 5 V x 300 x 10 = 1.03 H x 1. 8 V 13.2 V The inductor peak current is approximately 15 A + (5 A x 0.5) = 17.5 A Therefore, an appropriate inductor selection is 1.0 H with DCR = 3.3 m (Wurth Elektronik 7443552100) from Table 8 with peak current handling of 20 A. 2 PDCR( LOSS) = DCR x I L = 77.13 mW + 55.6 mW = 132.73 mW The rise in package temperature (for 10-lead MSOP) is TR = JA x PDR( LOSS ) = 171.2C x 132.05 mW = 22.7C Assuming a maximum ambient temperature environment of 85C, TJ = TR x TA = 22.7C + 85C = 107.72C which is below the maximum junction temperature of 125C. = 0.003 x (15 A)2 = 675 mW Current Limit Programming The valley current is approximately 15 A - (5 A x 0.5) = 12.5 A Assuming a lower-side MOSFET RON of 4.5 m and 13 A as the valley current limit from Table 7 and Figure 71 indicates, a programming resistor (RES) of 100 k corresponds to an ACS of 24 V/V. Choose a programmable resistor of RRES = 100 k for a currentsense gain of 24 V/V. DESIGN EXAMPLE The ADP1870/ADP1871 are easy to use, requiring only a few design criteria. For example, the example outlined in this section uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing), VIN = 12 V (typical), and fSW = 300 kHz. Input Capacitor The maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 V x 0.01 = 120 mV). VRIPP = 120 mV VMAX,RIPPLE = VRIPP - (ILOAD,MAX x ESR) = 120 mV - (15 A x 0.001) = 45 mV C IN,min = I LOAD, MAX 4 f SW V MAX , RIPPLE = 15 A 4 x 300 x 10 x 105 mV 3 Output Capacitor Assume that a load step of 15 A occurs at the output and no more than 5% is allowed for the output to deviate from the steady state operating point. In this case, the ADP1870's advantage is that because the frequency is pseudo-fixed, the converter is able to respond quickly because of the immediate, though temporary, increase in switching frequency. VDROOP = 0.05 x 1.8 V = 90 mV Assuming that the overall ESR of the output capacitor ranges from 5 m to 10 m, C OUT = 2 x = 2x I LOAD f SW x (VDROOP ) 15 A = 120 F Choose five 22 F ceramic capacitors. The overall ESR of five 22 F ceramic capacitors is less than 1 m. IRMS = ILOAD/2 = 7.5 A PCIN = (IRMS)2 x ESR = (7.5 A)2 x 1 m = 56.25 mW 300 x 10 3 x (90 mV) = 1.11 mF Therefore, an appropriate inductor selection is five 270 F polymer capacitors with a combined ESR of 3.5 m. Rev. 0 | Page 29 of 44 ADP1870/ADP1871 Assuming an overshoot of 45 mV, determine if the output capacitor that was calculated previously is adequate: C COMP = = 1 2RCOMP f ZERO C OUT = = ((VOUT (L x I LOAD ) - VOVSHT ) 2 - (VOUT )2 ) 2 1x 10 -6 x (15 A) 2 (1.8 - 45 mV) 2 - (1.8) 2 1 2 x 3.14 x 100 x 103 x 6.25 x 103 = 250 pF Loss Calculations Duty cycle = 1.8/12 V = 0.15 RON (N2) = 5.4 m tBODY(LOSS) = 20 ns (body conduction time) VF = 0.84 V (MOSFET forward voltage) CIN = 3.3 nF (MOSFET gate input capacitance) QN1,N2 = 17 nC (total MOSFET gate charge) RGATE = 1.5 (MOSFET gate input resistance) 2 PN1,N2(CL) = D x R N1(ON) + (1 - D ) x R N2(ON) x I LOAD = 1.4 mF Choose five 270 F polymer capacitors. The rms current through the output capacitor is 1 1 (V IN , MAX - VOUT ) VOUT I RMS = x x L x f SW V IN , MAX 2 3 1 1 (13.2 V - 1.8 V) 1.8 V =x x = 1.49 A 2 3 1 F x 300 x 10 3 13.2 V The power loss dissipated through the ESR of the output capacitor is PCOUT = (IRMS)2 x ESR = (1.5 A)2 x 1.4 m = 3.15 mW [ ] = (0.15 x 0.0054 + 0.85 x 0.0054) x (15 A)2 = 1.215 W x I LOAD x VF x 2 t SW = 20 ns x 300 x 103 x 15 A x 0.84 x 2 = 151.2 mW PSW(LOSS) = fSW x RGATE x CTOTAL x ILOAD x VIN x 2 = 300 x 103 x 1.5 x 3.3 x 10-9 x 15 A x 12 x 2 = 534.6 mW P DR ( LOSS ) = V DR x f SW C upperFET V DR + I BIAS + [V REG x ( f SW C lowerFET V REG + I BIAS Feedback Resistor Network Setup It is recommended to use RB = 15 k. Calculate RT as follows: RT = 15 k x (1.8 V - 0.6 V) 0.6 V = 30 k PBODY ( LOSS ) = t BODY ( LOSS ) Compensation Network To calculate RCOMP, CCOMP, and CPAR, the transconductance parameter and the current-sense gain variable are required. The transconductance parameter (GM) is 500 A/V, and the currentsense loop gain is G CS = 1 1 = = 8.33 A/V ACS RON 24 x 0.005 [ ( )] )] = ( 4 . 62 x (300 x 10 3 x 3 . 3 x 10 - 9 x 4 .62 + 0 . 002 )) + (5 . 0 x (300 x 10 3 x 3 . 3 x 10 - 9 x 5 . 0 + 0 . 002 )) = 57.12 mW where ACS and RON are taken from setting up the current limit (see the Programming Resistor (RES) Detect Circuit and Valley Current-Limit Setting sections). The crossover frequency is 1/12th of the switching frequency: 300 kHz/12 = 25 kHz The zero frequency is 1/4th of the crossover frequency: 25 kHz/4 = 6.25 kHz PDISS( LDO ) = (V IN - VREG ) x ( f SW x C total x VREG + I BIAS ) = (13 V - 5 V) x (300 x 10 3 x 3.3 x 10 -9 x 5 + 0.002) = 55.6 mW PCOUT = (IRMS)2 x ESR = (1.5 A)2 x 1.4 m = 3.15 mW 2 PDCR( LOSS) = DCR x I LOAD = 0.003 x (15 A)2 = 675 mW PCIN = (IRMS)2 x ESR = (7.5 A)2 x 1 m = 56.25 mW PLOSS = PN1,N2 + PBODY(LOSS) + PSW + PDCR + PDR + PDISS(LDO) + PCOUT + PCIN = 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW + 55.6 + 3.15 mW + 675 mW + 56.25 mW = 2.655 W RCOMP = = 2f CROSS C OUT VOUT f CROSS x x f CROSS + f ZERO G M G CS VREF 25 x 10 3 2 x 3.141 x 25 x 10 3 x 1.11 x 10 -3 1.8 x x 3 3 25 x 10 + 6.25 x 10 500 x 10 -6 x 8.3 0.6 = 100 k Rev. 0 | Page 30 of 44 ADP1870/ADP1871 EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 10 are with fCROSS = 1/12 x fSW, fZERO = 1/4 x fCROSS, RRES = 100 k, RBOT = 15 k, RON = 5.4 m (BSC042N03MS G), VREG = 5 V (float), and a maximum load current of 14 A. The ADP1871 models listed in Table 10 are the PSM versions of the device. Table 10. External Component Values Marking Code SAP Model ADP1870ARMZ-0.3-R7/ ADP1871ARMZ-0.3-R7 ADP1870 LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDX LDX LDX LDX LDX LDX LDX LDX LDX LDX LDX LDX LDX LDX LDX LDY LDY LDY LDY LDY LDY LDY LDY LDY LDY LDY LDY LDY ADP1871 LDG LDG LDG LDG LDG LDG LDG LDG LDG LDG LDG LDG LDG LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDN LDN LDN LDN LDN LDN LDN LDN LDN LDN LDN LDN LDN VOUT (V) 0.8 1.2 1.8 2.5 3.3 5 7 1.2 1.8 2.5 3.3 5 7 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 5 7 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 VIN (V) 13 13 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 5.5 5.5 5.5 5.5 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 5.5 5.5 5.5 5.5 13 13 13 13 13 16.5 16.5 16.5 16.5 CIN (F) 5 x 22 2 5 x 222 4 x 222 4 x 222 5 x 222 4 x 222 4 x 222 4 x 222 3 x 222 3 x 222 3 x 222 3 x 222 3 x 222 5 x 222 5 x 222 5 x 222 5 x 222 3 x 222 5 x 10 9 5 x 109 5 x 109 5 x 109 3 x 109 4 x 109 4 x 109 4 x 109 4 x 109 4 x 109 5 x 222 5 x 222 3 x 222 3 x 222 3 x 109 4 x 109 4 x 109 5 x 109 4 x 109 3 x 109 3 x 109 4 x 109 4 x 109 COUT (F) 5 x 560 3 4 x 5603 4 x 270 4 3 x 2704 2 x 330 5 3305 222 + ( 4 x 47 6 ) 4 x 5603 4 x 2704 4 x 2704 2 x 3305 2 x 150 7 222 + 4 x 476 4 x 5603 4 x 2704 3 x 2704 3 x 180 8 5 x 2704 3 x 3305 3 x 2704 2 x 2704 1507 4 x 2704 2 x 3305 3 x 2704 3305 4 x 476 3 x 476 4 x 2704 2 x 3305 3 x 1808 2704 3 x 3305 3 x 2704 2704 2704 3 x 476 4 x 2704 3 x 2704 3 x 1808 2704 L1 (H) 0.72 1.0 1.0 1.53 2.0 3.27 3.44 1.0 1.0 1.67 2.00 3.84 4.44 0.22 0.47 0.47 0.47 0.47 0.47 0.90 1.00 1.76 0.47 0.72 0.90 1.0 2.0 2.0 0.22 0.22 0.22 0.22 0.22 0.47 0.47 0.72 1.0 0.47 0.47 0.72 0.72 RC (k) 47 47 47 47 47 34 34 47 47 47 47 34 34 47 47 47 47 47 47 47 47 34 47 47 47 47 34 34 47 47 47 47 47 47 47 47 34 47 47 47 47 CCOMP (pF) 740 740 571 571 571 800 800 740 592 592 592 829 829 339 326 271 271 407 307 307 307 430 362 326 326 296 415 380 223 223 163 163 233 210 210 210 268 326 261 233 217 CPAR (pF) 74 74 57 57 57 80 80 74 59 59 59 83 83 34 33 27 27 41 31 31 31 43 36 33 33 30 41 38 22 22 16 16 23 21 21 21 27 33 26 23 22 RTOP (k) 5.0 15.0 30.0 47.5 67.5 110.0 160.0 15.0 30.0 47.5 67.5 110.0 160.0 5.0 15.0 30.0 47.5 15.0 30.0 47.5 67.5 110.0 15.0 30.0 47.5 67.5 110.0 160.0 5.0 15.0 30.0 47.5 15.0 30.0 47.5 67.5 110.0 15.0 30.0 47.5 67.5 ADP1870ARMZ-0.6-R7/ ADP1871ARMZ-0.6-R7 ADP1870ARMZ-1.0-R7/ ADP1871ARMZ-1.0-R7 Rev. 0 | Page 31 of 44 ADP1870/ADP1871 Marking Code SAP Model ADP1870 LDY LDY ADP1871 LDN LDN VOUT (V) 5 7 VIN (V) 16.5 16.5 CIN (F) 3 x 109 3 x 109 COUT (F) 3 x 476 222 + 476 L1 (H) 1.0 1.0 RC (k) 34 34 CCOMP (pF) 268 228 CPAR (pF) 27 23 RTOP (k) 110.0 160.0 1 2 See the Inductor Selection section and Table 11. 22 F Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm x 2.5 mm x 2.5 mm). 3 560 F Panasonic (SP-series) 2 V, 7 m, 3.7 A EEFUE0D561LR (4.3 mm x 7.3 mm x 4.2 mm). 4 270 F Panasonic (SP-series) 4 V, 7 m, 3.7 A EEFUE0G271LR (4.3 mm x 7.3 mm x 4.2 mm). 5 330 F Panasonic (SP-series) 4 V, 12 m, 3.3 A EEFUE0G331R (4.3 mm x 7.3 mm x 4.2 mm). 6 47 F Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm x 2.5 mm x 2.5 mm). 7 150 F Panasonic (SP-series) 6.3 V, 10 m, 3.5 A EEFUE0J151XR (4.3 mm x 7.3 mm x 4.2 mm). 8 180 F Panasonic (SP-series) 4 V, 10 m, 3.5 A EEFUE0G181XR (4.3 mm x 7.3 mm x 4.2 mm). 9 10 F TDK 25 V, X7R, 1210 C3225X7R1E106M. Table 11. Recommended Inductors L (H) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 DCR (m) 0.33 0.33 0.67 1.3 1.6 1.8 3.3 3.2 2.6 2.5 ISAT (A) 55 30 50 35 28 25 20 24 22 16.5 Dimension (mm) 10.2 x 7 10.2 x 7 13.2 x 12.8 10.5 x 10.2 13 x 12.8 10.5 x 10.2 10.5 x 10.2 14 x 12.8 13.2 x 10.8 12.5 x 12.5 Manufacturer Wurth Elektronik Wurth Elektronik Wurth Elektronik Wurth Elektronik Wurth Elektronik Wurth Elektronik Wurth Elektronik Wurth Elektronik Wurth Elektronik AIC Technology Model Number 744303012 744303022 744355147 744325072 744355090 744325120 7443552100 744318180 7443551200 CEP125U-R80 Table 12. Recommended MOSFETs VGS = 4.5 V Upper-Side MOSFET (Q1/Q2) RON (m) 5.4 10.2 6.0 9 5.4 10.2 6.0 ID (A) 47 53 19 14 47 82 19 VDS (V) 30 30 30 30 30 30 30 CIN (nF) 3.2 1.6 2.4 3.2 1.6 QTOTAL (nC) 20 10 35 25 20 10 35 Package PG-TDSON8 PG-TDSON8 SO-8 SO-8 PG-TDSON8 PG-TDSON8 SO-8 Manufacturer Infineon Infineon Vishay International Rectifier Infineon Infineon Vishay Model Number BSC042N03MS G BSC080N03MS G Si4842DY IRF7811 BSC042N03MS G BSC080N03MS G Si4842DY Lower-Side MOSFET (Q3/Q4) Rev. 0 | Page 32 of 44 ADP1870/ADP1871 LAYOUT CONSIDERATIONS The performance of a dc-to-dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (PCB). Optimizing the placement of sensitive analog and power components is essential to minimize output ripple, maintain tight regulation specifications, and reduce PWM jitter and electromagnetic interference. Figure 84 shows the schematic of a typical ADP1870/ADP1871 used for a high current application. Blue traces denote high current pathways. VIN, PGND, and VOUT traces should be wide and possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor. HIGH VOLTAGE INPUT VIN = 12V JP3 C28 10F CC 571pF RC 47k R1 30k R2 15k 3 4 5 CF 57pF VOUT ADP1870/ ADP1871 1 2 VIN COMP/EN FB GND VREG BST 10 SW 9 DRVH 8 PGND 7 DRVL 6 C12 100nF C3 22F Q1 Q2 C4 22F C5 22F C6 22F C7 22F C8 N/A C9 N/A 1.0H R4 0 R6 2 C13 1.5nF C20 270F + C21 270F VOUT = 1.8V, 15A + C22 270F + C23 270F + Q3 Q4 C2 0.1F C1 1F R5 100k C24 N/A + C25 N/A + C26 N/A + C27 N/A + C14 TO C19 N/A Figure 84. ADP1870 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths) Rev. 0 | Page 33 of 44 08730-081 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22F, 25V, X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 270F, SP-SERIES, 4V, 7m EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WURTH INDUCTORS: 1H, 3.3m, 20A 7443552100 ADP1870/ADP1871 SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER SECTION. SEPARATE ANALOG GROUND PLANE FOR THE ANALOG COMPONENTS (THAT IS, COMPENSATION AND FEEDBACK RESISTORS). BYPASS POWER CAPACITOR (C1) FOR VREG BIAS DECOUPLING AND HIGH FREQUENCY CAPACITOR (C2) AS CLOSE AS POSSIBLE TO THE IC. INPUT CAPACITORS ARE MOUNTED CLOSE TO DRAIN OF Q1/Q2 AND SOURCE OF Q3/Q4. OUTPUT CAPACITORS ARE MOUNTED ON THE RIGHTMOST AREA OF THE EVB, WRAPPING BACK AROUND TO THE MAIN POWER GROUND PLANE, WHERE IT MEETS WITH THE NEGATIVE TERMINALS OF THE INPUT CAPACITORS Figure 85. Overall Layout of the ADP1870 High Current Evaluation Board Rev. 0 | Page 34 of 44 08730-082 ADP1870/ADP1871 Figure 86. Layer 2 of Evaluation Board Rev. 0 | Page 35 of 44 08730-084 ADP1870/ADP1871 TOP RESISTOR FEEDBACK TAP Figure 87. Layer 3 of Evaluation Board Rev. 0 | Page 36 of 44 08730-083 VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK (SEE FIGURE 86 TO FIGURE 88). THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING BACK TO THE ANALOG PLANE (SEE FIGURE 88, LAYER 4 FOR PGND TAP). ADP1870/ADP1871 BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE PGND SENSE TAP FROM NEGATIVE TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE FROM FIGURE 84. Figure 88. Layer 4 (Bottom Layer) of Evaluation Board IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND). With the shortest path possible, connect the analog ground plane to the GND pin (Pin 4). This plane should be on only the top layer of the evaluation board. To avoid crosstalk interference, there should not be any other voltage or current pathway directly below this plane on Layer 2, Layer 3, or Layer 4. Connect the negative terminals of all sensitive analog components to the analog ground plane. Examples of such sensitive analog components include the resistor divider's bottom resistor, the high frequency bypass capacitor for biasing (0.1 F), and the compensation network. Mount a 1 F bypass capacitor directly across the VREG pin (Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 F should be tied across the VREG pin (Pin 5) and the GND pin (Pin 4). (yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns on. When Q3/Q4 turns on, the current direction continues to be maintained (red arrow) as it circles from the bulk capacitor's power ground terminal to the output capacitors, through the Q3/Q4. Arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through Q1/Q2 stops abruptly. Sudden changes in flux, usually at source terminals of Q1/Q2 and drain terminal of Q3/Q4, cause large dV/dt's at the SW node. The SW node is near the top of the evaluation board. The SW node should use the least amount of area possible and be away from any sensitive analog circuitry and components because this is where most sudden changes in flux density occur. When possible, replicate this pad onto Layer 2 and Layer 3 for thermal relief and eliminate any other voltage and current pathways directly beneath the SW node plane. Populate the SW node plane with vias, mainly around the exposed pad of the inductor terminal and around the perimeter of the source of Q1/Q2 and the drain of Q3/Q4. The output voltage power plane (VOUT) is at the rightmost end of the evaluation board. This plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminals of the output bulk capacitors. Ensure that the negative terminals of the output capacitors are placed close to the main power ground (PGND), as previously mentioned. All of these points form a tight circle POWER SECTION As shown in Figure 85, an appropriate configuration to localize large current transfer from the high voltage input (VIN) to the output (VOUT) and then back to the power ground is to put the VIN plane on the left, the output plane on the right, and the main power ground plane in between the two. Current transfers from the input capacitors to the output capacitors, through Q1/Q2, during the on state (see Figure 89). The direction of this current Rev. 0 | Page 37 of 44 08730-085 ADP1870/ADP1871 (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 - D. SW VOUT LAYER 1: SENSE LINE FOR SW (DRAIN OF LOWER MOSFET) LAYER 1: SENSE LINE FOR PGND (SOURCE OF LOWER MOSFET) Figure 90. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS Amp Differential Sensing (Yellow Sense Line on Layer 2) VIN PGND Figure 89. Primary Current Pathways During the On State of the Upper-Side MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow) DIFFERENTIAL SENSING Because the ADP1870/ADP1871 operate in valley currentmode control, a differential voltage reading is taken across the drain and source of the lower-side MOSFET. The drain of the lower-side MOSFET should be connected as close as possible to the SW pin (Pin 9) of the IC. Likewise, the source should be connected as close as possible to the PGND pin (Pin 7) of the IC. When possible, both of these track lines should be narrow and away from any other active device or voltage/current path. Differential sensing should also be applied between the outermost output capacitor to the feedback resistor divider (see Figure 87 and Figure 88). Connect the positive terminal of the output capacitor to the top resistor (RT). Connect the negative terminal of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane as well. Both of these track lines, as previously mentioned, should be narrow and away from any other active device or voltage/ current path. 08730-086 Rev. 0 | Page 38 of 44 08730-087 ADP1870/ADP1871 TYPICAL APPLICATIONS CIRCUITS 15 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 12V JP3 C28 10F CC 571pF RC 47k R1 30k R2 15k 3 4 5 CF 57pF VOUT ADP1870/ ADP1871 1 2 VIN COMP/EN FB GND VREG BST 10 SW 9 DRVH 8 PGND 7 C12 100nF C3 22F Q1 Q2 C4 22F C5 22F C6 22F C7 22F C8 N/A C9 N/A 1.0H R4 0 R6 2 C13 1.5nF C20 270F + C21 270F VOUT = 1.8V, 15A + C22 270F + C23 270F + Q3 Q4 DRVL 6 R5 100k C2 0.1F C1 1F C24 N/A + C25 N/A + C26 N/A + C27 N/A + C14 TO C19 N/A Figure 91. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect) 5.5 V INPUT, 600 kHz APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 5.5V JP3 C28 10F CC 571pF RC 47k R1 30k R2 15k 3 4 5 CF 57pF VOUT ADP1870/ ADP1871 1 2 VIN COMP/EN FB GND VREG BST 10 SW 9 DRVH 8 PGND 7 DRVL 6 C12 100nF C3 22F Q1 Q2 C4 22F C5 22F C6 22F C7 22F C8 N/A C9 N/A 0.47H R4 0 R6 2 C13 1.5nF C20 180F + C21 180F VOUT = 2.5V, 15A + C22 180F + C23 N/A + Q3 Q4 C2 0.1F C1 1F R5 100k C24 N/A + C25 N/A + C26 N/A + C27 N/A + C14 TO C19 N/A Figure 92. Application Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect) Rev. 0 | Page 39 of 44 08730-089 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22F, 25V, X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 180F, SP-SERIES, 4V, 10m EEFUE0G181XR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WURTH INDUCTORS: 0.47H, 0.8m, 50A 744355147 08730-088 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22F, 25V, X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 270F, SP-SERIES, 4V, 7m EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WURTH INDUCTORS: 1H, 3.3m, 20A 7443552100 ADP1870/ADP1871 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 13V JP3 C28 10F CC 528pF RC 43k R1 30k R2 15k 3 4 5 CF 53pF VOUT ADP1870/ ADP1871 1 2 VIN COMP/EN FB GND VREG BST 10 SW 9 DRVH 8 PGND 7 DRVL 6 C12 100nF C3 22F Q1 Q2 C4 22F C5 22F C6 N/A C7 N/A C8 N/A C9 270F 1.4H R4 0 R6 2 C13 1.5nF C20 270F + C21 270F VOUT = 1.8V, 12A + C22 270F + C23 270F + Q3 Q4 C2 0.1F C1 1F R5 100k C24 N/A + C25 N/A + C26 N/A + C27 N/A + C14 TO C19 N/A Figure 93. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect) Rev. 0 | Page 40 of 44 08730-090 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22F, 25V, X7R, 1210 GRM32ER71E226KE15L SANYO OSCON: 270F, 16SVPC270M, 14m PANASONIC: (OUTPUT CAPACITORS) 270F, SP-SERIES, 4V, 7m EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WURTH INDUCTORS: 0.72H, 1.65m, 35A 744325072 ADP1870/ADP1871 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 3.10 3.00 2.90 PIN 1 IDENTIFIER 1 5.15 4.90 4.65 5 0.50 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.30 0.15 15 MAX 1.10 MAX 0.70 0.55 0.40 091709-A 6 0 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 94. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP1870ARMZ-0.3-R7 ADP1870ARMZ-0.6-R7 ADP1870ARMZ-1.0-R7 ADP1871ARMZ-0.3-R7 ADP1871ARMZ-0.6-R7 ADP1871ARMZ-1.0-R7 ADP1870-0.3-EVALZ ADP1870-0.6-EVALZ ADP1870-1.0-EVALZ ADP1871-0.3-EVALZ ADP1871-0.6-EVALZ ADP1871-1.0-EVALZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding LDW LDX LDY LDG LDM LDN Z = RoHS Compliant Part. Rev. 0 | Page 41 of 44 ADP1870/ADP1871 NOTES Rev. 0 | Page 42 of 44 ADP1870/ADP1871 NOTES Rev. 0 | Page 43 of 44 ADP1870/ADP1871 NOTES (c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08730-0-3/10(0) Rev. 0 | Page 44 of 44 |
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